1. Field of the Invention
The present invention relates to an isolation method and a method of manufacturing a semiconductor device comprising the same. More particularly, the present invention relates to a self-aligned shallow trench isolation (SA-STI) technique that simultaneously forms a gate and an active region, and a method of manufacturing a non-volatile memory device comprising the same.
2. Description of the Related Art
During the manufacture of memory devices, the packing density of cells is primarily determined by the layout of cells within the array and the physical dimensions of the cells themselves. Below the half-micron design rule, scalability of the layout is limited by photolithographic resolution attainable during manufacturing and by alignment tolerances of masks used during production. Alignment tolerances are, in turn, limited by mechanical techniques employed to form masks and the techniques use to register these masks between layers. Because alignment errors accumulate during multi-stage fabrication, it is preferable to use as few masks as possible. Fewer masks minimize the likelihood of misalignment. Accordingly, xe2x80x9cself-alignmentxe2x80x9d processing steps have been developed to produce semiconductor devices.
Isolation structures between individual cells within the memory cell array consume regions of the chip that are otherwise useful for active circuitry. Thus, in order to increase the packing density of memory cell arrays within the substrate, it is desirable to minimize the size of these isolation structures. However, their process of formation and/or the alignment of the structures generally dictate the size of the isolation structure.
Typically, an isolation structure is grown at various regions of the chip by a thermal field oxidation process, such as a LOCal Oxidation of Silicon (hereinafter referred to as xe2x80x9cLOCOSxe2x80x9d). According to the LOCOS method, after a pad oxide layer and a nitride layer are successively formed, the nitride layer is subjected to patterning. Then, the patterned nitride layer is used as a mask to selectively oxidize the silicon substrate to form field oxide regions. However, in considering the LOCOS isolation, the growth of oxide may encroach upon the side plane of the pad oxide layer under the nitride layer serving as the mask during selective oxidation of the silicon substrate, thereby creating what is called a bird""s beak at the end portion of the field oxide layer. Due to the bird""s beak, the field oxide layer extends into the active region of the memory cell thereby decreasing the width of the active region. This phenomenon is undesirable because it degrades the electrical characteristics of the memory device.
For this reason, a shallow trench isolation (hereinafter referred to as xe2x80x9cSTIxe2x80x9d) structure is used in making ultra-high scale semiconductor devices. In the STI process, a silicon substrate is first etched to form a trench, and then an oxide layer is deposited to fill up the trench. Thereafter, the oxide layer is etched via an etch back or a chemical mechanical polishing (CMP) method so as to form a field oxide layer inside the trench.
The foregoing LOCOS and STI methods commonly include a mask step that defines the regions of the isolation structure on the substrate and a step that forms the field oxide layer within those regions. After forming the isolation structure, steps to form the memory cells are carried out. As such, alignment errors associated with forming the isolation structure and memory cells aggregate to induce mis-alignment, which may result in failure of the device.
When making a floating gate of a non-volatile memory device, for example, one method of reducing misalignment includes forming STI structure using a self-aligned floating gate, such as by the process disclosed in U.S. Pat. No. 6,013,551 (issued to Jong Chen, et al). According to the method described therein, a floating gate and active region thereof are simultaneously defined and fabricated using a single mask so that alignment errors do not aggregate.
Non-volatile memory devices have long-time storage capacity, e.g., almost indefinitely. In recent years, demand for such electrically erasable programmable read-only memory devices (EEPROMS) or flash EEPROMS has increased. Memory cells of these devices generally have a vertically stacked gate structure comprising a floating gate formed on the silicon substrate with a tunnel oxide layer interposed therebetween, and a control gate formed over and/or around the floating gate with a dielectric (or insulating) interlayer interposed therebetween. In a flash memory cell having this structure, data is stored by transferring electrons to and from the floating gate, which is achieved by applying a controlled voltage to the control gate and substrate. The dielectric interlayer functions to maintain the potential on the floating gate.
FIGS. 1A to 1E are perspective views of a substrate illustrating in succession a method of manufacturing a conventional flash memory device using a self-aligned STI technique. Referring to FIG. 1A, after forming an oxide layer 11 on a silicon substrate 10, a first polysilicon layer 13 and a nitride layer 15 are successively formed on the gate oxide layer 11. The oxide layer 11 serves as a tunnel oxide layer, i.e., a gate oxide layer, of the flash memory cell. The first polysilicon layer 13 serves as a floating gate. The nitride layer 15 serves as a polish-stopping layer during a subsequent chemical mechanical polishing process.
Referring to FIG. 1B, a photolithography process is performed to pattern the nitride layer 15, the first polysilicon layer 13, and the oxide layer 11 to form a nitride layer pattern 16, a first polysilicon layer pattern 14, and an oxide layer pattern 12. Thereafter, exposed portions of the substrate 10 are etched to a predetermined depth to form trenches 18. That is, the active regions and floating gates are simultaneously defined during the trench forming process using a single mask.
Referring to FIG. 1C, exposed portions of trenches 18 are subjected to thermal treatment in an oxygen atmosphere for curing silicon damages caused by high-energy ion bombardment during the trench etching process. By doing so, a trench inner-wall oxide layer 20 is formed along the inner surface including the bottom plane and sidewall of the trenches 18 by the oxidation reaction of the exposed silicon with an oxidant.
As widely known in the art, a reaction for forming an oxide layer is written as below:
Si+O2, H2Oxe2x86x92SiO2 
As noted from the above reaction, since the diffusion of oxygen into the layer having the silicon (Si) source effects oxidation of silicon, the oxidation reaction occurs at the interface between the first polysilicon layer pattern 14 and the oxide layer pattern 12, and at the interface between the oxide layer pattern 12 and the silicon substrate 10. On the contrary, since the amount of silicon in the edge portions of the first polysilicon layer pattern 14 is smaller than that in the other portions, an oxide layer is less grown on the edge portions than on the plane portions.
Therefore, the volume expansion due to the oxidation is limited on the edges of the interface between the first polysilicon layer pattern 14 and the oxide layer pattern 12 and the interface between the oxide layer pattern 12 and the silicon substrate 10. Since the stress due to the volume expansion is concentrated on these interface edges, the diffusion of oxygen progresses slowly to suppress the oxidation. As a result, because bottom edge portions of the first polysilicon layer pattern 14 are bent outward as shown in FIG. 2, the sidewalls of the first polysilicon layer pattern 14 have positive slope. Here, the positive slope denotes that the slope allows the sidewall erosion with respect to the etchant. In other words, as shown in the drawing, the intrusion of the oxidant into the portion underlying the nitride layer pattern 16 is blocked by the existence of nitride layer pattern 16 to provide the negative slope at the upper portion of the sidewall of the first polysilicon layer pattern 14. Meanwhile, the bottom edge portion of the lower portion of the first polysilicon layer pattern 14 is bent outward to have a positive slope, which is eroded by an etchant introduced from above the substrate in the same manner as in the sidewall of a mesa structure or to act as a stopping layer of the underlying layer when the etchant is applied, which is undesirable.
Referring to FIG. 1D, after forming an oxide layer (not shown) via a chemical vapor deposition (hereinafter referred to as xe2x80x9cCVDxe2x80x9d) method for filling up the trenches 18, the CVD-oxide layer is removed via a CMP process until the upper surface of nitride layer pattern 16 is exposed. As a result, a field oxide layer 22 is formed inside each of the trenches 18. After removing the nitride layer pattern 16 via a phosphoric acid stripping process, a second polysilicon layer 24 for the floating gate is deposited on the first polysilicon layer pattern 14 and the field oxide layer 22. The second polysilicon layer 24 makes contact with the first polysilicon layer pattern 14, and functions to increase the area of the dielectric interlayer that is formed in a subsequent process.
Thereafter, the second polysilicon layer over the field oxide layer 22 is partially etched via a photolithography process to form a second polysilicon layer pattern, and then an ONO dielectric interlayer 26 and a control gate 28 are successively formed on the entire surface of the resultant structure. The control gate 28 is generally formed by a polycide structure obtained by stacking a tungsten silicide layer on a doped polysilicon layer.
Referring to FIG. 1E, the control gate 28 is patterned via a photolithography process. Successively, the exposed dielectric interlayer 26 and the second and first polysilicon layer pattern 24 and 14 are anisotropically etched via a dry etch process. As a result, the stacked gate structure comprising the floating gate 25 consisting of the first and second polysilicon layer patterns 14 and 24 and the control gate 28 is formed on the memory cell region.
At this time, as shown in FIG. 1B, the lower portion of the sidewall of the first polysilicon layer pattern 14 has a positive slope. Therefore, by the characteristic of the anisotropic etching (i.e., where etching is performed only in the vertical direction) of the dry etch process, the bottom edge portion of the first polysilicon layer pattern 14 masked by the field oxide layer 22 is not etched to remain intact. As a result, a line-shaped polysilicon residue 14a is formed along the surface boundary of the active region and the field oxide layer 22. This polysilicon residue 14a forms an electrical bridge between adjacent floating gates, which causes an electrical failure of the device.
Therefore, it is an object of the present invention to provide a self-aligned shallow trench isolation method for preventing electrical failure of the device.
It is another object of the present invention to provide a method of manufacturing a non-volatile memory device that avoids a positive slope of the sidewalls of the floating gate.
In accordance with the method of the invention, an oxide layer is formed on a semiconductor substrate. A first conductive layer is formed on the oxide layer. A nitride layer is formed on the first conductive layer. The nitride layer, the first conductive layer and the oxide layer are etched by using a single mask to thereby form an oxide layer pattern, a first conductive layer pattern and a nitride layer pattern. By using this mask, the upper portion of the substrate adjacent to the first conductive layer pattern is etched away to form a trench. A CVD-oxide layer is deposited on the inner surface of the trench to form a trench inner-wall oxide layer. The trench inner-wall oxide layer is annealed in an N2O or NO atmosphere to form an oxynitride layer at the interface between the substrate and the trench inner-wall oxide layer. A field oxide layer is formed for filling up the trench.
In another aspect of the invention, an oxide layer for a gate oxide layer is formed on a semiconductor substrate. A first conductive layer for a floating gate layer is formed on the oxide layer. A nitride layer is formed on the first conductive layer. The nitride layer, the first conductive layer and the oxide layer are etched by using a single mask to thereby form an oxide layer pattern, a first conductive layer pattern and a nitride layer pattern. By using this mask, the upper portion of the substrate adjacent to the first conductive layer pattern is etched away to form a trench aligned to the first conductive layer pattern, thereby defining an active region of the substrate. Thereafter, a trench inner-wall oxide layer is formed by depositing a CVD-oxide layer on the inner surface portion of the trench to prevent the formation of a positive profile at the sidewalls of the first conductive layer pattern. The trench inner-wall oxide layer is annealed in N2O or NO atmosphere to form an oxynitride layer at the interface between the substrate and the trench inner-wall oxide layer. A field oxide layer is formed for filling up the trench. Finally, a dielectric interlayer and a control gate are formed successively on the first conductive layer pattern.
In one embodiment, the first conductive layer includes either polysilicon or amorphous silicon. The trench inner-wall oxide layer can be formed at a temperature of about 700 to 850xc2x0 C. the annealing in the N2O or NO atmosphere can be performed at a temperature of about 700 to 850xc2x0 C. The trench inner-wall oxide layer can be formed to a thickness of about 20 to 300 xc3x85.
In one embodiment formation of the trench inner-wall oxide layer and the annealing are performed in situ in a single reaction chamber. In an alternative embodiment, they are performed in separate chambers. In one embodiment, the field oxide layer is formed by forming a gap-fill oxide layer covering the nitride layer pattern while filling the trench and etching the gap-fill oxide layer to have a smooth surface by either chemical mechanical polishing or an etchback until the surface of the nitride layer pattern is exposed.
According to the present invention, the trench inner-wall oxide layer is formed by a chemical vapor deposition (CVD) to prevent the sidewalls of the first conductive layer pattern from having the positive slope. By doing so, conductive residue does not remain during a subsequent gate etching process, which prevents the failure of the device.
Further, after the above CVD process, the annealing for the densification of the CVD oxide is performed in an N2O or NO atmosphere to decrease the leakage current. In addition, the oxynitride layer is formed at the interface between the silicon substrate and the trench inner-wall oxide layer, to thereby enhance the interface charge characteristics and to prevent the out-diffusion of dopants from the active region adjacent to the trench.